Improving Datapath Testability by Modifying Controller Specification
نویسندگان
چکیده
منابع مشابه
Datapath Testability Improvement through ad hoc Controller Modifications
Even if a datapath has been synthesized with testability in view, its testability may strongly decreases once it is connected to its controller. In this paper, we propose controller modifications for restoring the testability of the datapath to a level close to the initial one. Those modifications concern the next state logic as well as the decoder part of the controller. The method is based on...
متن کاملImproving Circuit Testability by Clock Control
T h e testabili ty of a sequential circuit can be i m proved by controlling the clocks of individual storage elements during testing. W e propose several clock control strategies derived f r o m a n analysis of the circuit, i t s S-graph structure, and i ts funct ion. Through examples we show how the number of clocks aflects the circuit’s testability. It i s shown that if certain flip-flops (FF...
متن کاملImproving Testability and Reuse by Transitioning to Functional Programming
Declarative styles such as functional programming (FP) are rapidly gaining ground on their imperative cousins, including procedural and object-oriented programming. The shift is subtle because it is happening within the context of multiparadigm programming languages such as JavaScript. FP is better suited to modern processes like test-driven development (TDD), and architectures like massively p...
متن کاملController and Datapath ‘ IYade - offs in Hierarchical RT - Level Synthesis
We intend to study the impact of control logic on the RT-kvel design space of a class of digital systems. Such an enhancement of the design space is more accurate than several prm”OUSIYreported approaches since control logic has a sz”gnijicant impact on the total cost and petiormance of the circuit. We present a datapath synthesis j?amework that is hierarchical in nature; and thus allows the co...
متن کاملLow overhead DFT using CDFG by modifying controller
Abstract: A novel design-for-test (DFT) method that requires minor modifications to the controller in the register-transfer level (RTL) description of a circuit is presented. The control/data flow graph representation of an RTL circuit is used for analysing the testability of individual RTL operations within the RTL circuit. Using a non-scan arrangement, existing data paths are utilised to prov...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: VLSI Design
سال: 2002
ISSN: 1065-514X,1563-5171
DOI: 10.1080/1065514021000012101